Sub-station

power supply rejection for low- jitter clocks

by:KEBO      2019-11-26
1.
The usual challenge for hardware designers is to increase functional density while reducing the overall PCB footprint of each new design.An important challenge is to minimize clock jitter with careful board design while meeting design features and space requirements.Since jitter is a measure of signal fidelity, in order to manage the impact of jitter on performance, it needs to understand various simulation concepts such as transmission line theory, interference, bandwidth, and noise.Among them, the density has the greatest influence on the sensitivity of external noise and interference.Since noise and interference are everywhere, and since multiple components share a common power supply, the power supply is the direct path in which noise and interference affect the jitter performance of each device.Therefore, achieving the lowest clock jitter requires careful management of the power supply.The sensitivity to the power supply is often referred to as the power supply ripple suppression or the power supply rejection ratio (PSRR ).For jitter, ripple suppression is more appropriate.
2.
The effect of power ripple on jitter is very simple.The power supply affects the propagation delay by affecting the switching voltage threshold and output resistance of the logic gate.When the switching voltage threshold is modulated, the time when the output conversion is modulated due to the limited slope of the input signal.
The change in the output resistance affects the propagation delay of the CMOS gate through the parasitic RC filter.When the two effects are combined, the propagation delay is changed through the CMOS gate.This effect is amplified as more doors are placed in series.
The degree of influence depends highly on the \"speed\" of the transistor involved \".By having a faster slope at the CMOS gate input, the impact of the change threshold can be minimized.In addition, in order to achieve a small propagation delay, a faster circuit requires minimizing the capacitance;Therefore, by making the routing capacitance as small as possible, the delay change caused by the power change can be minimized.However, there is trade-offs;The disadvantage of a faster circuit is power consumption.In order to get a faster edge, more current is needed to charge the capacitor at a given constant voltage.
3.
The common ways to reduce the power sensitivity are power filtering and minimizing the circuit sensitivity.
3.1.
External and internal methods are often used to manage the power ripple suppression of the integrated circuit.Externally, board designers use active and passive filters to decay ripple and differential interfaces to reject common-mode ripple.Internally, architecture selection, linear regulators, and differential circuits are used to reduce circuit sensitivity to the power supply.
Direct filtering of the power supply can be achieved using a passive filter or a linear regulator.Common external filter solutions depend on ferrite beads and discrete surfaces-To install ceramic capacitors using this method, the series resistance must be minimized to avoid reducing the supply voltage of the IC.
Unfortunately, the filtering is highly dependent on the series impedance (resistance and resistance );Therefore, it is necessary to ensure that the iron bead can handle the device current.The linear regulator can also filter the power supply noise by using the regulator as a high levelpass filter.Typically, these technologies are combined to provide filtering throughout the focus.
Depending on the desired level of performance and the cost objectives associated with a given design, costs and power transactions should be taken into account --Off associated with external filtering.Ferrite beads are much cheaper than active regulators and hardly waste power, but they cannot reach the same level of filtering as regulators at low frequencies.Therefore, beforeThe design evaluation of timing hardware should include the power supply ripple suppression test.
Differential circuits help to suppress power noise by allowing power interference to occur in public mode and eliminating interference by subtracting public modemode signal.Since the power ripple will reduce the positive and negative legs, they will accumulate noise together.
Power noise is rejected by subtracting these signals.What is to be considered here is the receiver\'s ability to suppress common mode noise.This is called common-Pattern ripple suppression (CMRR ).As in the CMOS gate, a quick rise/fall time can help.
External filtering may be necessary for designs that do not support differential signaling.Many timing devices with CMOS/TTL interfaces cannot take into account the power ripple.The system designer should verify the ripple suppression on the workbench.
3.2.
When affected by the power ripple, architecture selection also plays a role in ensuring good jitter performance.Timing equipment usually depends on phaseLock Loops (PLLs) that perform various functions, such as jitter filtering and frequency multiplication.One of the main challenges in loop design is its voltage-Controllable oscillator (VCO ).In order to meet the frequency requirements of various applications, it is usually necessary to have a wide tuning range oscillator, but the oscillator jitter is proportional to the noise of its control input (usually its most sensitive port.In order to reduce jitter, it is necessary to use low jitterGain control input, but the lower limit of the gain is damaged by the desired frequency range and the frequency of the oscillator (E.G.g.Process changes, temperature, strain, etc.) This gain limitation can be overcome by new circuit technology, such as the circuit technology adopted by the Silicon Lab dsp ll.™Technology.Using digitalVariable control-Gain oscillator;The dsp ll can provide a large tuning range and low gain, thus minimizing its sensitivity during operation.
In addition, most timing integrated circuits work at low supply voltage (less than 5 v.With the reduction of the process geometry, the voltage is reduced, and the tuning range of the control port is also limited.In order to achieve all the output frequencies, Tuning Port gain must be increased.In addition, the tuning signal amplitude is relative to noise (I.e., reduced SNR).Higher gain and lower signal-to-noise ratio result in poor jitter performance.It is critical to select a timing device, such as a device that uses a DSP LL™Silicon Labs that solve these problems.
DSP LL™Low support at the same timeBy using a digital interface for its controlled oscillator, the voltage supplies and improves the signal-to-noise ratio.Regardless of the supply voltage level, the digital interface allows the SNR to remain high and the gain is set to any low.Since the tuning range is not limited by the supply voltage, the signal-to-noise ratio is still high.Other architectural options are also helpful: eliminating VCOs can completely eliminate concerns about tuning gain and interference.Multi-synthesis technology in Silicon LaboratoryEach IC uses only one VCO for simultaneous frequency synthesis on multiple outputs.By using only one VCO, the Silicon Lab improves the functional density without increasing the interference.
4.
Benchmarking system performance can be as difficult as building in ripple suppression.There are two common challenges.First, the power supply has a low impedance in order to maintain a constant voltage without considering the load; secondly, jitter/phase noise test equipment usually only supports \\ \"singleAnalog signal, not differential and/or rail-to-Track signal related to high levelPerformance timing circuit.In order to correctly evaluate jitter performance, the requirements for low-impedance power rails and letters must be considered.
Having a low impedance network for analysis means implementing the desired ripple voltage (E.G.g.100 mVpp) and high current sources are not common.To place a constant voltage ripple signal on a node with low impedance, the ripple source needs to have a high drive strength.An easy way to achieve sufficient DC current required for the operation of the device and sufficient AC current required to generate ripple is to obtain these requirements from a separate power supply.This separation can be achieved by using a standard power supply and AC coupling in parallel with a sine signal source (ripple source.The ripple source requires a high impedance when it is DC to avoid absorbing a large amount of current from the power supply and has the potential to damage the ripple source.Since the impedance is a function of the frequency, the low impedance is also a vague description.
Therefore, in order to achieve a constant ripple voltage, the ripple source must be adjusted for each interference frequency.The phase of the ripple signal is often ignored because it does not provide actionable data (I.e.The goal is to limit the magnitude of the chain reaction;Therefore, focus on the amplitude response ).Overcome the single-Use a differential amplifier or a limiting amplifier.Phase noise (I.e., Jitter) complicated by amplitude noise, must be separated.Limit amplifier reject public-Mode interference makes the spectrum report only the phase response.
Relative power is expressed in decibels (dB) and in units as dBc (decibels relative to carrier power) relative to the output frequency (carrier ).Since the limiting amplifier eliminates most of the amplitude noise and interference, it is possible to assume the measuring sideThe Spurs can be attributed to phase jitter.This allows direct measurement of RMS jitter caused by the ripple source.Equation 1 shows the edge-With relative power and RMS jitter.After setting the ripple voltage to the desired level, the Spurs will measure it within the desired frequency range.
(-59.
Equation 1.RMS jitter calculated for phase
4.1.
A common scenario to consider is that in the range of 10 kHz to 3 MHz, the 100 mVpp positive string ripple produces jitter.This comparison was made with Si530 XO products and competitive products from Silicon Labs.
5.
The power ripple suppression performance depends on the internal power filtering and architecture selection in the timing integrated circuit.Designers can evaluate timing ic with simple frequency scanning and compare devices with constant ripple voltage.This comparison can help designers choose the best equipment for their systems, which is especially important when performance differences are high.
Custom message
Chat Online 编辑模式下无法使用
Chat Online inputting...